Upcoming AMD SP5 socket will support up to 12TB of memory

Upcoming AMD SP5 socket will support up to 12TB of memory

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The upcoming SP5 socket for the AMD EPYC Genoa processors has conscionable been leaked, showing the committee successful its afloat glory, implicit with 12-channel DDR5 enactment and 128 PCIe Gen 5.0 lanes.

This means that the motherboard volition enactment a whopping 12TB of strategy representation alongside a tremendously almighty information halfway processor.

AMD SP5 socket pictured.111alan

Although AMD EPYC Genoa is yet to beryllium released, it’s connected way to motorboat this year, and according to AMD, the archetypal samples of the CPU were already sent retired to customers. That explains however a representation of the matching caller SP5 socket motherboard had been leaked by a ServerTheHome (STH) forum member.

The caller socket volition usher successful the adjacent procreation of AMD EPYC processors, including some Genoa (set to merchandise successful 2022) and Bergamo (2023). Looking astatine the committee successful its afloat glory shows the staggering amounts of powerfulness that a machine of that size requires successful 2022 and beyond.

The pictured SP5 socket comes with 6,096 onshore grid array (LGA) interaction pads, a monolithic upgrade implicit the current-gen SP3 with conscionable 4,094 contacts. What we’re seeing successful the photograph is really a dual 2P level with 2 SP5 sockets, adding up to a full of 24 dual in-line representation module (DIMM) slots.

In total, a azygous committee volition enactment 12-channel DDR5 memory. This means that the upcoming AMD Genoa could beryllium paired with up to 12TB representation connected conscionable 1 motherboard. Calling that an awesome fig would beryllium an understatement, and the numbers lone get bigger from here.

AMD EPYC Zen 4 Genoa processors.Image source: VideoCardz VideoCardz

Upping the fig of representation channels is simply a sizeable upgrade for AMD EPYC, which has antecedently supported up to eight, and present receives an further four. Of course, the erstwhile SP3 socket lone supported DDR4 representation — this meant that the capableness maxed retired astatine 4TB per chip. With the power to DDR5 representation offered by SP5, that volition ascent up to 12TB. However, arsenic Wccftech points out, 3D stacked DIMMs volition person to beryllium utilized successful bid to execute this benignant of capacity.

AMD EPYC Genoa volition beryllium the archetypal AMD information halfway processor to enactment DDR5 representation and PCIe Gen 5.0. The spot volition diagnostic a monolithic 96 cores and 192 threads and it volition beryllium made based connected TSMC’s 5nm technology. The spot itself has already been leaked earlier and it’s enormous, arsenic tin beryllium expected from a processor of this power.

The maximum socket TDP volition beryllium rated astatine 700 watts. Circling backmost to RAM, Genoa volition enactment not conscionable a batch of it, but it volition beryllium speedy arsenic well: The SP5 socket allows for the usage of DDR5-5200 memory. Although Genoa is already impressive, its successor, Bergamo, volition bring the numbers higher still, maxing retired astatine 128 cores portion inactive utilizing the aforesaid SP5 socket.

No authoritative merchandise dates person been announced arsenic of yet, but we bash cognize that AMD EPYC Genoa is expected to motorboat this year. Sapphire Rapids Xeon, which is Intel’s counterpart of the AMD Genoa, is besides releasing successful 2022 with DDR5 and PCIe Gen 5.0 support.

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